LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 111

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
6.1.2
REGISTER NAME
MAC_CSR_DATA
MAC_CSR_CMD
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
FREE_RUN
PMT_CTRL
GPIO_CFG
E2P_DATA
RX_DROP
GPT_CFG
GPT_CNT
AFC_CFG
E2P_CMD
HW_CFG
RX_CFG
TX_CFG
ENDIAN
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9118, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met.
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
Table 6.1 Read After Write Timing Rules (continued)
FOLLOWING ANY WRITE CYCLE
MINIMUM WAIT TIME FOR READ
DATASHEET
(IN NS)
Table 6.2
135
315
135
180
45
45
45
45
45
45
45
45
45
45
45
45
0
0
111
Table 6.2, "Read After Read Timing
also shows the number of dummy reads that are
(ASSUMING T
NUMBER OF BYTE_TEST
READS
Revision 1.1 (05-17-05)
CYCLE
1
1
1
1
0
3
7
1
1
3
1
4
0
1
1
1
1
1
Rules". The host
OF 45NS)