LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 114

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
6.4
SYMBOL
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
ah
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
In this mode the upper address inputs are not decoded, and any read of the LAN9118 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9118. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit Direct PIO Read cycles is identical with the exception that D[31:16] is not
driven during a 16-bit read. Note that address lines A[2:1] are still used, and address bits A[7:3] are
ignored.
RX Data FIFO Direct PIO Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Table 6.4 PIO Burst Read Timing
DATASHEET
114
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
13
45
0
0
0
0
TYP
MAX
30
40
7
SMSC LAN9118
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns