LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 36

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
3.9.2.2
3.9.2.3
3.9.2.4
EEDIO (OUTPUT)
EEDIO (INPUT)
EECLK
EECS
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit
is set if the EEPROM does not respond within 30ms.
Table 3.8, "Required EECLK
each EEPROM operation.
MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.
If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be
un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates
a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC
address.
EEPROM Command and Data Registers
Refer to
"E2P_DATA – EEPROM Data Register," on page 91
Supported EEPROM operations are described in these sections.
EEPROM Timing
Refer to
OPERATION
ERASE
WRITE
EWDS
EWEN
WRAL
READ
ERAL
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 89
Section 6.9, "EEPROM Timing," on page 119
1
0
0
Figure 3.10 EEPROM WRAL Cycle
Table 3.8 Required EECLK Cycles
0
Cycles", shown below, shows the number of EECLK cycles required for
1
DATASHEET
36
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
D7
REQUIRED EECLK CYCLES
for detailed EEPROM timing specifications.
for a detailed description of these registers.
D0
10
10
10
10
18
18
18
t
CSL
and
Section 5.3.24,
SMSC LAN9118
Datasheet