LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 115

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
6.5
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
FIFO_SEL
nCS, nRD
A[2:1]
Data Bus
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
In this mode the upper address inputs are not decoded, and any burst read of the LAN9118 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9118. Timing
RX Data FIFO Direct PIO Burst Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Table 6.5 RX Data FIFO Direct PIO Read Timing
DATASHEET
115
MIN
45
32
13
0
0
0
0
TYP
Revision 1.1 (05-17-05)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns