LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 116

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
SYMBOL
t
t
t
t
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
ah
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines.
In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD or
WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS)
or Read Enable (nRD). When either or both of these control signals go high, they must remain high
for the period specified.
Timing for 16-bit and 32-bit RX Data FIFO Direct PIO Burst Reads is identical with the exception that
D[31:16] are not driven during a 16-bit burst. Note that address lines A[2:1] are still used, and address
bits A[7:3] are ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
DATASHEET
116
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
13
45
0
0
0
0
TYP
MAX
30
40
7
SMSC LAN9118
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns