PEB2085 SIEMENS [Siemens Semiconductor Group], PEB2085 Datasheet - Page 266

• Manufacturer Part Number: PEB2085
• Description: ISDN SubscribernAccess Controller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Description of the receive PLL (RPLL) of the ISAC-S
The receive PLL performs phase tracking each 250 s after detecting the phase between the
F/L transition of the receive signal and the recovered clock. Phase adjustment is done by
adding or subtracting 130 ns to or form a 1.536-MHz clock cycle. The 1.536-MHz clock is than
used to generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz and 512-kHz
clocks to have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC output
in TE mode is set to a specific phase relationship, thus causing once an irregular FSC timing.
Reset
Table 34
Reset Signal Characteristics
Parameter
Length of active
high state
Figure 106
Semiconductor Group
RST
Symbol
t
RST
Limit Values
min.
4
2
clock cycles
DCL
266
t
RST
Unit
ms
Test Condition
Power on/Power Down
to Power Up (Standby)
During Power Up (Standby)
PEB 2086
ITD02396