PEB2085 SIEMENS [Siemens Semiconductor Group], PEB2085 Datasheet - Page 75

no-image

PEB2085

Manufacturer Part Number
PEB2085
Description
ISDN SubscribernAccess Controller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2085-P
Manufacturer:
SIEMENS/西门子
Quantity:
20 000
Part Number:
PEB2085N
Manufacturer:
SIEMENS
Quantity:
5 510
Part Number:
PEB2085N
Manufacturer:
ALLEGRO
Quantity:
5 510
Part Number:
PEB2085N
Manufacturer:
LNFINEON
Quantity:
20 000
Part Number:
PEB2085N V2.3
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
PEB2085NV1.1
Manufacturer:
PHI
Quantity:
399
Part Number:
PEB2085NV1.1
Manufacturer:
SIE
Quantity:
1 000
Part Number:
PEB2085NV1.1
Manufacturer:
SIE
Quantity:
20 000
Part Number:
PEB2085NV2.3
Manufacturer:
SIEMENS
Quantity:
5 967
Part Number:
PEB2085NV2.3
Manufacturer:
SIE
Quantity:
1 000
Part Number:
PEB2085NV2.3
Manufacturer:
SIEMENS/西门子
Quantity:
20 000
Part Number:
PEB2085P
Quantity:
41
Part Number:
PEB2085P
Manufacturer:
SIEMENS
Quantity:
1 000
2) A second C/I channel (called C/I1) can be used to convey real time status information
Semiconductor Group
non-TE). It can be accessed by an external layer-2 device e.g. to control the layer-1
activation/deactivation procedures. C/I0 channel access may be arbitrated via the TIC bus
access protocol in the IOM-2 terminal timing mode (SPCR:SPM=0). In this case the
arbitration is done in C/I channel 2 (see figure 29).
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2) and
register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits long.
A listing and explanation of the layer-1 C/I codes can be found in chapter 3.4.
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
being generated anytime a change occurs (ISTA:CISQ). A new code must be found in two
consecutive IOM frames to be considered valid and to trigger a C/I code change interrupt
status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
between the ISAC-S and various non-layer-1 peripheral devices e.g. PSB 2160 ARCOFI.
The channel consists of six bits in each direction. It is available only in the IOM-2 TE timing
mode (see figure 29).
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received C/I1
code is indicated by an interrupt status without double last look criterion.
75
Functional Description

Related parts for PEB2085