PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 146

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
10.6
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is
controlled by the 4 upper bits of the TRISE register
(Register 10-1).
(TRISE<4>), enables PSP operation, as long as the
Enhanced CCP1 (ECCP1) module is not operating in
dual output or quad output PWM mode. In Slave mode,
the port is asynchronously readable and writable by the
external world.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit, PSPMODE, enables the PORTE I/O
pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For
this functionality, the corresponding data direction bits
of the TRISE register (TRISE<2:0>) must be config-
ured as inputs (set). The A/D port configuration bits,
PFCG3:PFCG0 (ADCON1<3:0>), must also be set to
‘1010’.
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
When either the CS or RD line is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
DS39761B-page 144
Note:
Parallel Slave Port
The Parallel Slave Port is only available on
PIC18F4682/4685 devices.
Setting
control
bit,
PSPMODE
Preliminary
The timing for the control signals in Write and Read
modes is shown in Figure 10-3 and Figure 10-4,
respectively.
FIGURE 10-2:
Note:
Set Interrupt Flag
PSPIF (PIR1<7>)
Data Bus
WR LATD or
WR PORTD
RD PORTD
RD LATD
I/O pins have diode protection to V
One bit of PORTD
Data Latch
D
Q
CK
EN
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
EN
Q
D
© 2007 Microchip Technology Inc.
Select
Read
Write
Chip
DD
TTL
and V
TTL
TTL
TTL
PORTE Pins
SS
.
RDx pin
CS
WR
RD