PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 479

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

Timing Diagrams and Specifications ................................ 435
© 2007 Microchip Technology Inc.
SPI Mode (Slave Mode with CKE = 1) ..................... 194
Stop Condition Receive or Transmit Mode .............. 220
Synchronous Reception
Synchronous Transmission ...................................... 242
Synchronous Transmission
Time-out Sequence on POR w/PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 439
Transition for Entry to Idle Mode ................................ 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
Transition for Wake From Idle
Transition for Wake From Sleep (HSPLL) ................. 37
Transition From RC_RUN Mode
Transition From SEC_RUN Mode
Transition to RC_RUN Mode ..................................... 36
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 437
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
(Master Mode, SREN) ..................................... 244
(Through TXEN) .............................................. 243
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 355
to PRI_RUN Mode ............................................. 36
to PRI_RUN Mode (HSPLL) .............................. 35
Internal RC Accuracy ....................................... 436
(All CCP Modules) ........................................... 440
Requirements .................................................. 450
Requirements .................................................. 450
(Master Mode, CKE = 0) .................................. 442
(Master Mode, CKE = 1) .................................. 443
(Slave Mode, CKE = 0) .................................... 444
to Run Mode ..................................................... 38
DD
, V
DD
DD
DD
), Case 1 ....................... 46
), Case 2 ....................... 46
Rise Tpwrt) ................ 46
DD
) ............................. 47
PIC18F2682/2685/4682/4685
Preliminary
Top-of-Stack Access .......................................................... 62
TRISE Register
TSTFSZ ........................................................................... 403
Two-Speed Start-up ................................................. 343, 355
Two-Word Instructions
TXSTA Register
V
Voltage Reference Specifications .................................... 431
W
Watchdog Timer (WDT) ........................................... 343, 353
WCOL ...................................................... 215, 216, 217, 220
WCOL Status Flag ................................... 215, 216, 217, 220
WWW Address ................................................................ 478
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 403
XORWF ........................................................................... 404
Example SPI Mode Requirements
External Clock Requirements .................................. 435
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 436
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External
PSPMODE Bit ......................................................... 138
Example Cases ......................................................... 66
BRGH Bit ................................................................. 231
Associated Registers ............................................... 354
Control Register ....................................................... 353
Programming Considerations .................................. 353
2
2
C Bus Data Requirements (Slave Mode) .............. 447
C Bus Start/Stop Bits Requirements
(Slave Mode, CKE = 1) .................................... 445
(Slave Mode) ................................................... 446
Requirements .................................................. 448
(PIC18F4682/4685) ......................................... 441
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 438
Clock Requirements ........................................ 439
2
2
C Bus Data Requirements ................ 449
C Bus Start/Stop Bits
DS39761B-page 477