PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 360

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
24.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other PIC
devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 24-5:
DS39761B-page 358
Program Verification and
Code Protection
(PIC18F2682/4682)
Unimplemented
Unimplemented
Boot Block
80 Kbytes
Read ‘0’s
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
Block 4
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2682/2685/4682/4685
(PIC18F2685/4685)
Unimplemented
96 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Preliminary
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
010000h
013FFFh
014000h
017FFFh
018000h
1FFFFFh
Address
Range
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-5 shows the program memory organization
for 80- and 96-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
(Unimplemented Memory Space)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
CP4, WRT4, EBTR4
CP5, WRT5, EBTR5
Controlled By:
© 2007 Microchip Technology Inc.