PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 476

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PIC18F2682-I/PT

Manufacturer Part Number
PIC18F2682-I/PT
Description
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
PIC18F2682/2685/4682/4685
PWM (ECCP1 Module) .................................................... 175
Q
Q Clock .................................................................... 170, 176
R
RAM. See Data Memory.
RC Oscillator ...................................................................... 25
RC_IDLE Mode .................................................................. 39
RC_RUN Mode .................................................................. 35
RCALL .............................................................................. 393
RCON Register
Reader Response ............................................................ 479
Register File Summary ................................................. 76–86
Registers
DS39761B-page 474
Auto-Shutdown ........................................................ 170
Direction Change in Full-Bridge
Duty Cycle ................................................................ 176
ECCPR1H:ECCPR1L Registers .............................. 175
Effects of a Reset ..................................................... 185
Enhanced Mode ....................................................... 175
Enhanced PWM Auto-Shutdown ............................. 182
Example Frequencies/Resolutions .......................... 176
Full-Bridge Application Example .............................. 180
Full-Bridge Mode ...................................................... 179
Half-Bridge Mode ..................................................... 178
Half-Bridge Output Mode Applications
Output Configurations .............................................. 176
Output Relationships (Active-High) .......................... 177
Output Relationships (Active-Low) ........................... 177
Period ....................................................................... 175
Programmable Dead-Band Delay ............................ 182
Setup ........................................................................ 185
Start-up Considerations ........................................... 184
TMR2 to PR2 Match ................................................ 175
RCIO Oscillator Mode ................................................ 25
Bit Status During Initialization .................................... 48
ADCON0 (A/D Control 0) ......................................... 247
ADCON1 (A/D Control 1) ......................................... 248
ADCON2 (A/D Control 2) ......................................... 249
BAUDCON (Baud Rate Control) .............................. 230
BIE0 (Buffer Interrupt Enable 0) ............................... 319
BnCON (TX/RX Buffer n Control,
BnCON (TX/RX Buffer n Control,
BnDLC (TX/RX Buffer n Data Length Code
BnDLC (TX/RX Buffer n Data Length Code
BnDm (TX/RX Buffer n Data Field Byte m
BnDm (TX/RX Buffer n Data Field Byte m
BnEIDH (TX/RX Buffer n Extended Identifier,
BnEIDH (TX/RX Buffer n Extended Identifier,
BnEIDL (TX/RX Buffer n Extended Identifier,
BnSIDH (TX/RX Buffer n Standard Identifier,
BnSIDH (TX/RX Buffer n Standard Identifier,
Output Mode .................................................... 180
Example ........................................................... 178
Receive Mode) ................................................. 295
Transmit Mode) ................................................ 296
in Receive Mode) ............................................. 301
in Transmit Mode) ............................................ 302
in Receive Mode) ............................................. 300
in Transmit Mode) ............................................ 300
High Byte in Receive Mode) ............................ 299
High Byte in Transmit Mode) ........................... 299
Low Byte in Receive Mode) ..................... 299, 300
High Byte in Receive Mode) ............................ 297
High Byte in Transmit Mode) ........................... 297
Preliminary
BnSIDL (TX/RX Buffer n Standard Identifier,
BRGCON1 (Baud Rate Control 1) ........................... 312
BRGCON2 (Baud Rate Control 2) ........................... 313
BRGCON3 (Baud Rate Control 3) ........................... 314
BSEL0 (Buffer Select 0) ........................................... 302
CCP1CON (Capture/Compare/PWM Control) ......... 163
CIOCON (CAN I/O Control) ..................................... 315
CMCON (Comparator Control) ................................ 257
COMSTAT (CAN Communication Status) ............... 281
CONFIG1H (Configuration 1 High) .......................... 344
CONFIG2H (Configuration 2 High) .......................... 346
CONFIG2L (Configuration 2 Low) ........................... 345
CONFIG3H (Configuration 3 High) .......................... 347
CONFIG4L (Configuration 4 Low) ........................... 347
CONFIG5H (Configuration 5 High) .......................... 348
CONFIG5L (Configuration 5 Low) ........................... 348
CONFIG6H (Configuration 6 High) .......................... 350
CONFIG6L (Configuration 6 Low) ........................... 349
CONFIG7H (Configuration 7 High) .......................... 351
CONFIG7L (Configuration 7 Low) ........................... 351
CVRCON (Comparator Voltage
DEVID1 (Device ID 1) .............................................. 352
DEVID2 (Device ID 2) .............................................. 352
ECANCON (Enhanced CAN Control) ...................... 280
ECCP1AS (Enhanced Capture/Compare/PWM
ECCP1CON (Enhanced
ECCP1DEL (PWM Dead-Band Delay) .................... 182
EECON1 (Data EEPROM Control 1) ................. 97, 106
HLVDCON (High/Low-Voltage
INTCON (Interrupt Control) ...................................... 115
INTCON2 (Interrupt Control 2) ................................. 116
INTCON3 (Interrupt Control 3) ................................. 117
IPR1 (Peripheral Interrupt Priority 1) ....................... 124
IPR2 (Peripheral Interrupt Priority 2) ....................... 125
IPR3 (Peripheral Interrupt Priority 3) ............... 126, 318
MSEL0 (Mask Select 0) ........................................... 308
MSEL1 (Mask Select 1) ........................................... 309
MSEL2 (Mask Select 2) ........................................... 310
MSEL3 (Mask Select 3) ........................................... 311
OSCCON (Oscillator Control) .................................... 30
OSCTUNE (Oscillator Tuning) ................................... 27
PIE1 (Peripheral Interrupt Enable 1) ........................ 121
PIE2 (Peripheral Interrupt Enable 2) ........................ 122
PIE3 (Peripheral Interrupt Enable 3) ................ 123, 317
PIR1 (Peripheral Interrupt
PIR2 (Peripheral Interrupt
PIR3 (Peripheral Interrupt
RCON (Reset Control) ....................................... 42, 127
RCSTA (Receive Status and Control) ..................... 229
RXB0CON (Receive Buffer 0 Control) ..................... 288
RXB1CON (Receive Buffer 1 Control) ..................... 290
RXBnDLC (Receive Buffer n
RXBnDm (Receive Buffer n
RXBnEIDH (Receive Buffer n
Low Byte in Receive Mode) ............................. 298
Reference Control) .......................................... 263
Auto-Shutdown Configuration) ........................ 183
Capture/Compare/PWM Control) .................... 173
Detect Control) ................................................ 267
Request (Flag) 1) ............................................. 118
Request (Flag) 2) ............................................. 119
Request (Flag) 3) ..................................... 120, 316
Data Length Code) .......................................... 293
Data Field Byte m) ........................................... 293
Extended Identifier, High Byte) ........................ 292
© 2007 Microchip Technology Inc.

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