PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 189

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

17.0
17.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode
17.2
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual Configuration bits
differ significantly depending on whether the MSSP
module is operating in SPI or I
Additional details are provided under the individual
sections.
© 2007 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
2
C)
2
C mode.
PIC18F2682/2685/4682/4685
Preliminary
17.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/HLVDIN
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
RA5/AN4/SS/HLVDIN
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
SPI Mode
of
SPI
are
Read
SS Control
Enable
MSSP BLOCK DIAGRAM
(SPI MODE)
SMP:CKE
bit 0
supported.
Select
Edge
Select
Edge
SSPBUF reg
SSPSR reg
SSPM3:SSPM0
2
Data to TX/RX in SSPSR
TRIS bit
Clock Select
4
DS39761B-page 187
2
To
(
Prescaler
4, 16, 64
TMR2 Output
Write
accomplish
Clock
Shift
Internal
Data Bus
2
T
OSC
)