PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 298

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE
DS39761B-page 296
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
TXBIF
R/W-0
2:
3:
4:
5:
(3)
These registers are available in Mode 1 and 2 only.
Clearing this bit in software while the bit is set will request a message abort.
This bit is automatically cleared when TXREQ is set.
While TXREQ is set or transmission is in progress, transmit buffer registers remain read-only.
These bits set the order in which the transmit buffer will be transferred. They do not alter the CAN
message identifier.
TXBIF: Transmit Buffer Interrupt Flag bit
1 = A message is successfully transmitted
0 = No message was transmitted
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits
0 = Automatically cleared when the message is successfully sent
RTREN: Automatic Remote Transmission Request Enable bit
1 = When a remote transmission request is received, TXREQ will be automatically set
0 = When a remote transmission request is received, TXREQ will be unaffected
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
TXABT
R-0
[0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1]
(3)
W = Writable bit
‘1’ = Bit is set
TXLARB
R-0
(3)
TXERR
R-0
Preliminary
(2,4)
(3)
(5)
(3)
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXREQ
R/W-0
(1)
(3)
(3)
(2,4)
RTREN
R/W-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
TXPRI1
R/W-0
(5)
TXPRI0
R/W-0
bit 0
(5)