PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 451

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 27-21: MASTER SSP I
© 2007 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
Maximum pin capacitance = 10 pF for all I
A Fast mode I
parameter 107 ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for
100 kHz mode), before the SCL line is released.
:
:
:
:
:
STA
DAT
STO
STA
DAT
Clock High
Time
Clock Low Time 100 kHz mode
SDA and SCL
Rise Time
SDA and SCL
Fall Time
Start Condition
Setup Time
Start Condition
Hold Time
Data Input
Hold Time
Data Input
Setup Time
Stop Condition
Setup Time
Output Valid
from Clock
Bus Free Time
Bus Capacitive Loading
2
C™ bus device can be used in a Standard mode I
Characteristic
2
100 kHz mode
400 kHz mode
1 MHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
C™ BUS DATA REQUIREMENTS
PIC18F2682/2685/4682/4685
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Preliminary
2
C pins.
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
20 + 0.1 C
20 + 0.1 C
Min
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
250
100
4.7
1.3
—
—
—
—
—
—
—
—
0
0
B
B
1000
3500
1000
Max
2
300
300
300
300
100
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C bus system, but
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
10 to 400 pF
C
10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the first
clock pulse is generated
(Note 2)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
Conditions
DS39761B-page 449