LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 102

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

Note :
17.4.19 CR14
17.4.20 CR15
17.4.21 CR16 – CR20
Revision 0.3 (10-26-04)
Writing CR13 changes the Configuration Ports base address.
This register is reserved, read only, and returns 0 when read.
CR15 can only be accessed in the configuration state and after the CSR has been initialized to 15H. CR15
shadows the bits in the write-only UART run-time FCR register.
These registers are reserved, read only, and return 0 when read.
BIT NO.
BIT NO.
3-7
4,5
6,7
0
1
2
0
1
2
3
RCVR Trigger
FIFO Enable
RCVR FIFO
DMA Mode
XMIT FIFO
Type : R/W
Type: R/W
BIT NAME
BIT NAME
Reserved
Reserved
Select
Reset
Reset
A10
A8
A9
Configuration Ports Base Address Byte 1 (Note)
Configuration Ports Base Address Byte 1 for decoder.
Read Only. A read returns 0.
Setting this bit to a logic "1" enables both the XMIT and RCVR
FIFOs
Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and
resets its counter logic to 0. This bit is self clearing.
Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and
resets its counter logic to 0. This bit is self-clearing.
Writing to this bit has no effect on the operation of the UART.
Read Only. A read returns 0.
These bits are used to set the trigger level for the RCVR FIFO
interrupt.
UART FCR Shadow Register
DATASHEET
BIT7
0
0
1
1
Table 17.15 – CR13
Table 17.16 - CR15
Page 102
BIT6
0
1
0
1
Default : 0x00 (SYSOPT=0)
RCVR FIFO TRIGGER LEVEL (BYTES)
DESCRIPTION
DESCRIPTION
3.3v I/O Controller for Port Replicators and Docking Stations
0x00 (SYSOPT=1)
on VCC POR and HARD RESET
Default: N/A
14
1
4
8
SMSC DS – LPC47N237