LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 103

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
17.4.22 CR21
17.4.23 CR22
Note :
17.4.24 CR23
SMSC DS – LPC47N237
CR21 can only be accessed in the configuration state and after the CSR has been initialized to 21H.
The ECP Software Select register CR22 contains the ECP IRQ Select bits and the ECP DMA Select bits.
CR22 is part of the ECP DMA/IRQ Software Indicators described in the ECP cnfgB register. CR22 is
read/write.
All of the ECP DMA/IRQ Software Indicators, including CR22, are software-only. Writing these bits does
not affect the ECP hardware DMA or IRQ channels that are configured in CR26 and CR27.
CR23 can only be accessed in the configuration state and after the CSR has been initialized to 23H. CR23
is used to select the base address of the parallel port. If EPP is not enabled, the parallel port can be set to
192 locations on 4-byte boundaries from 100H - 3FCH; if EPP is enabled, the parallel port can be set to 96
locations on 8-byte boundaries from 100H - 3F8H. To disable the parallel port, set ADR9 and ADR8 to
zero.
Parallel Port Address Decoding: address bits A[15:10] must be ‘000000’ to access the Parallel Port when
in Compatible, Bi-directional, or EPP modes. A10 is active when in ECP mode.
BIT NO.
BIT NO.
3-7
0,1
2:0
5:3
6,7
2
ECP DMA Select ECP DMA software Indicator
TIMEOUT_SELECT
ECP IRQ Select
Type: R/W
Type: R/W
BIT NAME
Reserved
BIT NAME
Reserved
Reserved
ECP Software Select Register
ECP IRQ Software Indicator
Read Only. A read returns 0.
DATASHEET
Read Only. A read returns 0.
This bit selects the means of clearing the TIMEOUT bit in the
EPP Status register. If the TIMEOUT_SELECT bit is cleared
(‘0’), the TIMEOUT bit is cleared on the trailing edge of the read
of the EPP Status Register (default).
If the TIMEOUT_SELECT bit is set (‘1’), the TIMEOUT bit is
cleared on a write of ‘1’ to the TIMEOUT bit.
Read Only. A read returns 0.
EPP Timeout Select
Table 17.17 – CR21
Table 17.18 - CR22
Page 103
Default: 0x00 on VCC POR and HARD RESET
DESCRIPTION
DESCRIPTION
Default: 0x00 on VCC POR
Revision 0.3 (10-26-04)