LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 28

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

7.3.3
Revision 0.3 (10-26-04)
SYNC Error Indication
The LPC47N237 reports errors via the LAD[3:0] = 1010 SYNC encoding.
If the host was reading data from the LPC47N237, data will still be transferred in the next two nibbles. This
data may be invalid, but it will be transferred by the LPC47N237. If the host was writing data to the
LPC47N237, the data had already been transferred.
In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if
the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the
other three bytes will not be transferred.
I/O and DMA START Fields
I/O and DMA cycles use a START field of 0000.
Reset Policy
The following rules govern the reset policy:
1.
2.
LPC Transfers
Wait State Requirements
I/O Transfers
The LPC47N237 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A
SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would be
deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used
and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us).
DMA Transfers
The LPC47N237 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A
SYNC of 0101 is used for all DMA transfers.
See the example timing for the LPC cycles in the “Timing Diagrams” section.
When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior
to the removal of the reset signal, so that everything is stable. This is the same reset active time after
clock is stable that is used for the PCI bus.
When nPCI_RESET goes active (low):
a)
b)
the host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ
the LPC47N237 ignores nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal
signal.
inactive (high).
DATASHEET
Page 28
3.3v I/O Controller for Port Replicators and Docking Stations
SMSC DS – LPC47N237