LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 32

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

Revision 0.3 (10-26-04)
MODE
ONLY
BIT 3
FIFO
CPU access, even if the Serial Port records new interrupts, the current indication does not change until
access is completed. The contents of the IIR are described below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt
is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a
pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the
Interrupt Control Table.
Bit 3
In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout
interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic "0".
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
0
0
0
1
BIT 2
IDENTIFICATION
0
1
1
1
INTERRUPT
REGISTER
BIT 1
0
1
0
0
BIT 0
1
0
0
0
Table 8.2 – UART Interrupt Control Table
Highest
Second
Second
PRIORITY
LEVEL
DATASHEET
-
INTERRUPT SET AND RESET FUNCTIONS
None
Receiver Line
Status
Received
Data
Available
Character
Timeout
Indication
Page 32
INTERRUPT
TYPE
3.3v I/O Controller for Port Replicators and Docking Stations
None
Overrun Error,
Parity Error,
Framing Error or
Break Interrupt
Receiver Data
Available
No Characters
Have Been
Removed From or
Input to the
RCVR FIFO
during the last 4
Char times and
there is at least 1
char in it during
this time
INTERRUPT
SOURCE
Reading the Line
Status Register
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
Reading the
Receiver Buffer
Register
INTERRUPT
CONTROL
RESET
SMSC DS – LPC47N237
-