MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 161

• Manufacturer Part Number: MC68HC912D60A
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

SLOW — Slow mode Divider Register
MC68HC912D60A — Rev 3.0
MOTOROLA
RESET:
Bit 7
0
0
6
0
0
Read and write anytime.
A write to this register changes the SLWCLK frequency with minimum
delay (less than one SLWCLK cycle), thus allowing immediate tune-
up of the performance versus power consumption for the modules
using this clock. The frequency divide ratio is 2 times (SLOW), hence
the divide range is 2 to 126 (not on first pass products). When
SLOW = 0, the divider is bypassed. The generation of E, P and
M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus
to EXTALi Frequency is programmable to 2, 4, 8, 12, 16, 20, ..., 252,
by steps of 4. SLWCLK is a 50% duty cycle signal.
Freescale Semiconductor, Inc.
For More Information On This Product,
SLDV5
5
0
Go to: www.freescale.com
SLDV4
Clock Functions
4
0
SLDV3
3
0
Limp-Home and Fast STOP Recovery modes
SLDV2
2
0
SLDV1
1
0
SLDV0
Bit 0
0
Clock Functions
Technical Data
$003E
161