MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 250
MC68HC912D60A
Manufacturer Part Number
MC68HC912D60A
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912D60A.pdf
(460 pages)
- Current page: 250 of 460
- Download datasheet (4Mb)
Enhanced Capture Timer
ICPACR — Input Control Pulse Accumulators Control Register
Technical Data
250
RESET:
BIT 7
0
0
6
0
0
POLF3 – POLF0 — First Input Capture Polarity Status
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if
PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN
have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if
PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN
have no effect.
Read: any time
Write: any time
PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable
These are read only bits. Write to these bits has no effect.
Each status bit gives the polarity of the first edge which has caused
an input capture to occur after capture latch has been read.
Each POLFx corresponds to a timer PORTx input.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
0 = 8-Bit Pulse Accumulator is disabled.
1 = 8-Bit Pulse Accumulator is enabled.
5
0
0
Go to: www.freescale.com
Enhanced Capture Timer
4
0
0
PA3EN
3
0
PA2EN
2
0
PA1EN
MC68HC912D60A — Rev 3.0
1
0
PA0EN
BIT 0
0
MOTOROLA
$00A8
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