MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 300

• Manufacturer Part Number: MC68HC912D60A
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Motorola Interconnect Bus
SC0SR2 — MI Bus Status Register 2
Technical Data
300
RESET:
SCSWAI
Bit 7
0
MIE
OR — Bit Error Flag
NF — Noise Error Flag
6
0
Read anytime. Write has no meaning or effect.
SCSWAI — Serial Communications Interface Stop in WAIT Mode
MIE — Motorola Interface Bus (MI Bus) Enable
MDL1, MDL0 — MI Bus delay select
This bit is set when a push field bit value on the MI Bus does not
match the bit value that was sent. This is known as an MI Bus bit
error. OR does not generate an interrupt request in MI Bus mode.
This bit is set when noise is detected on the receive line during an
MI Bus pull field.
When MIE is set, the SCI0 registers, bits and pins assume the
functionality required for MI Bus.
These bits are used to set up the delay for the start of the NRZ receive
for MI Bus operation as shown (for a 20kHz bit rate) in the following
table.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = No bit error has been detected.
1 = A bit error has been detected.
0 = No noise detected.
1 = Noise detected.
0 = SCI clock operates normally.
1 = Halt SCI clock generation when in WAIT mode.
0 = The SCI functions normally.
1 = MI Bus is enabled for this subsystem.
MDL1
5
0
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Motorola Interconnect Bus
MDL0
4
0
3
0
0
2
0
0
MC68HC912D60A — Rev 3.0
1
0
0
Bit 0
RAF
0
MOTOROLA
$00C5