MC68HC912D60A MOTOROLA [Motorola, Inc], MC68HC912D60A Datasheet - Page 198
MC68HC912D60A
Manufacturer Part Number
MC68HC912D60A
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912D60A.pdf
(460 pages)
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Oscillator
12.5.1.3 Bias Current Process Optimization
12.5.1.4 Input ESD Resistor Path Modification
Technical Data
198
For proper oscillation, the gain margin of the oscillator must exceed one
or the circuit will not oscillate. Process variance in the bias current (which
controls the gain of the amplifier) can cause the gain margin to be much
lower than typical. This can be as a result of either too much or too little
current.
To reduce the process sensitivity of the gain, the material of the device
that sets the bias current was changed to a material with tighter process
and temperature control. As a result, the transconductance and Ibias
variances are more limited than in the previous design.
To satisfy the condition of oscillation, the oscillator circuit must not only
provide the correct amount of gain but also the correct amount of phase
shift. In the Pierce configuration, the phase shift due to parasitics in the
input path to the gate of the transconductance amplifier must be as low
as possible. In the original configuration, the parasitic capacitance of the
clock input buffer (OTA), automatic Loop Control circuit (ALC), and input
resistor (RFLT) reacted with the input resistance to cause a large phase
shift.
To reduce the phase shift, the input ESD resistor (marked RESD in the
figure above) was changed from a single path to the input circuitry (the
ALC and the OTA) and oscillator transconductance amplifier (marked
GM in the figure above) to a parallel path. In this configuration, the only
capacitance causing a phase shift on the input to the transconductance
device is due to the transconductance device itself.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Oscillator
MC68HC912D60A — Rev 3.0
MOTOROLA
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