HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 160

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HD64F3670

Manufacturer Part Number
HD64F3670
Description
Hitachi Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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11.4
The timer W has the following operating modes.
11.4.1
TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free-
running counter. When the CST bit in TMRW is set to 1, TCNT starts incrementing the count.
When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE
in TIERW is set to 1, an interrupt request is generated. Figure 11.2 shows free-running counting.
Periodic counting operation can be performed when GRA is set as an output compare register and
bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the
IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt
request is generated. TCNT continues counting from H'0000. Figure 11.3 shows periodic
counting.
Rev. 2.0, 03/02, page 136 of 298
Normal Operation
PWM Operation
Operation
Normal Operation
H'FFFF
H'0000
CST bit
OVF
TCNT value
Figure 11.2 Free-Running Counter Operation
Flag cleared
by software
Time

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