HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 202

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

13.5.3
Figure 13.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
7. The SCK3 pin is fixed high.
Figure 13.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Rev. 2.0, 03/02, page 178 of 298
Figure 13.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
TDRE
TEND
LSI
operation
User
processing
been written to TDR, and transfers the data from TDR to TSR.
this time, a transmit data empty interrupt (TXI) is generated.
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD
pin.
of the next frame is started.
Serial
clock
Serial
data
the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt
request is generated.
Serial Data Transmission
TXI interrupt
request
generated
Bit 0
Bit 1
TDRE flag
cleared
to 0
Data written
to TDR
1 frame
TXI interrupt request generated
Bit 7
Bit 0
Bit 1
1 frame
Bit 6
TEI interrupt request
generated
Bit 7