HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 173

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

11.6
The following types of contention or operation can occur in timer W operation.
1. The pulse width of the input clock signal and the input capture signal must be at least two
2. Writing to registers is performed in the T2 state of a TCNT write cycle.
3. Depending on the timing, TCNT may be incremented by a switch between different internal
4. If timer W enters module standby mode while an interrupt request is generated, the interrupt
system clock ( ) cycles; shorter pulses will not be detected correctly.
If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 11.24. If counting-up is
generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes
precedence.
clock sources. When TCNT is internally clocked, an increment pulse is generated from the
rising edge of an internal clock signal, that is divided system clock ( ). Therefore, as shown in
figure 11.25 the switch is from a low clock signal to a high clock signal, the switchover is seen
as a rising edge, causing TCNT to increment.
request cannot be cleared. Before entering module standby mode, disable interrupt requests.
Usage Notes
Address
Write signal
Counter clear
signal
TCNT
Figure 11.24 Contention between TCNT Write and Clear
TCNT write cycle
N
TCNT address
T1
T2
H'0000
Rev. 2.0, 03/02, page 149 of 298