HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 20

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 13.16 Sample Multiprocessor Serial Transmission Flowchart ...................................... 186
Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (1)...................................... 188
Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (2)...................................... 189
Figure 13.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 190
Figure 13.19 Receive Data Sampling Timing in Asynchronous Mode..................................... 193
Section 14 A/D Converter
Figure 14.1 Block Diagram of A/D Converter ........................................................................ 196
Figure 14.2 A/D Conversion Timing...................................................................................... 202
Figure 14.3 External Trigger Input Timing............................................................................. 203
Figure 14.4 A/D Conversion Accuracy Definitions (1) ........................................................... 204
Figure 14.5 A/D Conversion Accuracy Definitions (2) ........................................................... 205
Figure 14.6 Analog Input Circuit Example............................................................................. 206
Section 15 Power Supply Circuit
Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used ................... 207
Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used............. 208
Section 17 Electrical Characteristics
Figure 17.1 System Clock Input Timing................................................................................. 233
# $
Figure 17.2
Low Width Timing ..................................................................................... 233
Figure 17.3 Input Timing....................................................................................................... 233
Figure 17.4 SCK3 Input Clock Timing .................................................................................. 234
Figure 17.5 SCI3 Input/Output Timing in Clocked Synchronous Mode................................... 234
Figure 17.6 Output Load Circuit ............................................................................................ 235
Appendix B I/O Port Block Diagrams
Figure B.1 Port 1 Block Diagram (P17) ................................................................................. 267
Figure B.2 Port 1 Block Diagram (P14) ................................................................................. 268
Figure B.3 Port 1 Block Diagram (P16, P15, P12, P10) .......................................................... 269
Figure B.4 Port 1 Block Diagram (P11) ................................................................................. 270
Figure B.5 Port 2 Block Diagram (P22) ................................................................................. 271
Figure B.6 Port 2 Block Diagram (P21) ................................................................................. 272
Figure B.7 Port 2 Block Diagram (P20) ................................................................................. 273
Figure B.8 Port 5 Block Diagram (P57, P56).......................................................................... 274
Figure B.9 Port 5 Block Diagram (P55) ................................................................................. 275
Figure B.10 Port 5 Block Diagram (P54 to P50)..................................................................... 276
Figure B.11 Port 7 Block Diagram (P76) ............................................................................... 277
Figure B.12 Port 7 Block Diagram (P75) ............................................................................... 278
Figure B.13 Port 7 Block Diagram (P74) ............................................................................... 279
Figure B.14 Port 8 Block Diagram (P84 to P81)..................................................................... 280
Figure B.15 Port 8 Block Diagram (P80) ............................................................................... 281
Figure B.16 Port B Block Diagram (PB3 to PB0)................................................................... 282
Rev. 2.0, 03/02, page xviii of xxii