HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 66

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HD64F3670

Manufacturer Part Number
HD64F3670
Description
Hitachi Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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3.1
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Relative Module Exception Sources
5(6
Watchdog timer
External interrupt
pin
CPU
Address break
CPU
External interrupt
pin
Timer W
Timer V
SCI3
A/D converter
Rev. 2.0, 03/02, page 42 of 298
pin
Exception Sources and Vector Address
Reset
Reserved for system use
NMI
Trap instruction (#0)
Break conditions satisfied
Direct transition by executing the
SLEEP instruction
IRQ0
IRQ3
WKP
Reserved for system use
Input capture A/compare match A
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Timer W overflow
Timer V compare match B
Timer V overflow
SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
A/D conversion end
Timer V compare match A
(#1)
(#2)
(#3)
25
Vector
Number Vector Address
0
1 to 6
7
8
9
10
11
12
13
14
17
18
20
21
22
23
H'0000 to H'0001
H'0002 to H'000D
H'0018 to H'0019
H'001A to H'001B
H'0024 to H'0025
H'0028 to H'0029
H'002A to H'002B
H'002C to H'002D
H'002E to H'002F
H'0032 to H'0033
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0014 to H'0015
H'0016 to H'0017
H'001C to H'001D
H'0022 to H'0023
Priority
High
Low

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