HD64F3670 RENESAS [Renesas Technology Corp], HD64F3670 Datasheet - Page 210

• Manufacturer Part Number: HD64F3670
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

13.6.1
Figure 13.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
Rev. 2.0, 03/02, page 186 of 298
[1]
[2]
[3]
Multiprocessor Serial Data Transmission
Figure 13.16 Sample Multiprocessor Serial Transmission Flowchart
Clear PDR to 0 and set PCR to 1
Write transmit data to TDR
Clear TE bit in SCR3 to 0
Read TDRE flag in SSR
Read TEND flag in SSR
Set MPBT bit in SSR
All data transmitted?
Start transmission
Break output?
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
No
Yes
No
No
No
[1]
[2]
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Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR3 to 0.