NAND04G-B2D NUMONYX [Numonyx B.V], NAND04G-B2D Datasheet
NAND04G-B2D
Related parts for NAND04G-B2D
NAND04G-B2D Summary of contents
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... Chip Enable ‘don’t care’ ■ Serial number option December 2007 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. NAND04G-B2D, NAND08G-BxC 4 Gbit, 8 Gbit, 2112 byte/1056 word page TSOP48 (N) r ■ Data protection: – ...
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... Write Enable ( 3.8 Write Protect (WP 3.9 Ready/Busy (RB 3.10 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DD 3.11 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.1 6.1.2 6.2 Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/69 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 NAND04G-B2D, NAND08G-BxC ...
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... NAND04G-B2D, NAND08G-BxC 6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 6.3.2 6.4 Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.7 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.8 Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.9 Error detection code (EDC 6.10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.11 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.12 Read status enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.13 Read EDC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.14 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.15 Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.16 Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 Concurrent operations and extended read status ...
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... Contents 11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 63 12.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/69 NAND04G-B2D, NAND08G-BxC ...
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... NAND04G-B2D, NAND08G-BxC List of tables Table 1. Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Address insertion (x8 devices Table 7. Address insertion (x16 devices Table 8. Address definition (x8 devices Table 9. Address definition (x16 devices Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11. ...
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... List of figures List of figures Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. TSOP48 connections for NAND04G-B2D and NAND08G-BxC . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. LGA52 connections for NAND04G-B2D and NAND08G-B2C devices Figure 5. LGA52 connections for the NAND08G-B4C devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. ...
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... Flash memories. They use NAND cell technology have a density of 4 Gbits and 8 Gbits, respectively. The NAND04G-B2D memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time (one in each plane erase 2 blocks at a time (one in each plane). This feature reduces the average program and erase times by 50% ...
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... For more information on these two options, contact your nearest Numonyx Sales office. The devices are available in the TSOP48 ( mm) and LGA52 ( mm) packages. To meet environmental requirements, Numonyx offers the NAND04G-B2D and NAND08G- BxC in ECOPACK For information on how to order these options, refer to scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’ ...
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... NAND04G-B2D, NAND08G-BxC Figure 1. Logic block diagram Address Register/Counter Command Interface E Logic WP R Command Register 1. The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die. Figure 2. Logic diagram 1. The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die. ...
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... Write Protect V Supply Voltage DD V Ground SS NC Not connected internally DU Do not use 1. The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die. 10/69 (1) Function NAND04G-B2D, NAND08G-BxC Direction Input/output Input/output Input Input Input Input Output Input Input Power supply Ground N/A N/A ...
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... NAND04G-B2D, NAND08G-BxC Figure 3. TSOP48 connections for NAND04G-B2D and NAND08G-BxC NAND FLASH Description I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI13168b 11/69 ...
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... Description Figure 4. LGA52 connections for NAND04G-B2D and NAND08G-B2C devices 12/ I/O0 I/O1 NC I/O2 I/ NAND04G-B2D, NAND08G-BxC I/O7 I/ I/O5 I/ ...
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... NAND04G-B2D, NAND08G-BxC Figure 5. LGA52 connections for the NAND08G-B4C devices The NAND08G-B4C devices have two separate sets of signals for each 4 Gb die I/O0 2 I/O0 1 I/O1 1 I/O1 2 I/O2 1 I/O3 1 ...
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... Table 4. Valid Blocks Density of Device 4 Gbits 8 Gbits 1. The NAND08G-BxC devices are composed of two 4-Gbit dice. The minimum number of valid blocks is 4016 for each die. 14/69 organization. Section 9: Software Min 4016 (1) 8032 NAND04G-B2D, NAND08G-BxC Section 9.1: Bad block algorithms). Max 4096 8192 ...
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... NAND04G-B2D, NAND08G-BxC Figure 6. Memory array organization Plane = 2048 blocks, block = 64 pages, page = 2112 bytes (2048 + 64) Main area Block Page 2048 bytes Page buffer, 2112 bytes Plane = 2048 blocks, block = 64 pages, page = 1056 words (1024 + 32) Main area Block Page 1024 words Page buffer, 1056 bytes ...
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... The Read Enable pin, R, controls the sequential data output during read operations. Data is valid t after the falling edge of R. The falling edge of R also increments the internal RLQV column address counter by one. 16/69 NAND04G-B2D, NAND08G-BxC and Table 3: Signal names for a brief overview of the signals , the device is selected. If Chip Enable goes IL ...
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... NAND04G-B2D, NAND08G-BxC 3.7 Write Enable (W) The Write Enable input, W, controls writing to the Command Interface, input address and data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 10 µs (min) is required before the command interface is ready to accept a command ...
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... The data is output sequentially using the Read Enable signal. 18/69 for a summary of these operations. Table 30 for details of the timings requirements. Table 6: Address insertion (x8 devices) Table 30 for details of the timings requirements. Table 30 and Table 31 for details of the timings requirements. NAND04G-B2D, NAND08G-BxC and Table 7: Address ...
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... NAND04G-B2D, NAND08G-BxC If the Read Enable pulse frequency is lower then 33 MHz (t output data is latched on the rising edge of Read Enable signal (see For higher frequencies (t used. In this mode, data output bus operations are valid on the input/output bus for a time of t after the falling edge of Read Enable signal (see ...
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... A13 A12 A22 A21 A20 (2) V A29 A28 IL Definition Column address Page address Block address(NAND04G-B2D) Block address (NAND08G-BxC) First plane Second plane Definition Column address Page address Block address (NAND04G-B2D) Block address (NAND08G-BxC) First plane Second plane I/ A11 A19 A27 ...
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... NAND04G-B2D, NAND08G-BxC 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security ...
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... The sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the Random Data Output command. The Random Data Output command can be issued as many times as required within a page. The Random Data Output command is not accepted during cache read operations. 22/69 NAND04G-B2D, NAND08G-BxC Table 10: Commands). (see Table 31 ) ...
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... NAND04G-B2D, NAND08G-BxC Figure 7. Read operations I/O Address Input 00h Command Code tBLBH1 30h Data Output (sequentially) Command Busy Code Device operations ai12469 23/69 ...
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... Busy tRHWL 05h Data Output Cmd Code Col Add 1,2 Spare Area Section 6.1.1: Random NAND04G-B2D, NAND08G-BxC Address E0h Data Output Inputs Cmd Code 2 Add cycles Spare Main Area Area read, is issued prior to the and Figure 10: Cache read (random) ...
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... NAND04G-B2D, NAND08G-BxC After the Sequential Cache Read or Random Cache Read command has been issued, the Ready/Busy signal goes Low and the Status Register bits are set to SR5 =' 0' and SR6 ='0' for a period of Cache Read busy time, t Cache Register. After the cache read busy time has passed, the Ready/Busy signal goes High and the Status Register bits are set to SR5 = '0' and SR6 = '1', signifying that the Cache Register is ready to download new data ...
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... Once the program operation has completed, the P/E/R Controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the command interface. 26/69 and Table 7: Address insertion (x16 for more information. devices)). NAND04G-B2D, NAND08G-BxC Table 6: devices)). 3. Table 10: Table 6: ...
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... NAND04G-B2D, NAND08G-BxC Figure 11. Page program operation RB I/O 80h Page Program Setup Code Figure 12. Random data input during sequential data input RB Address I/O 80h Data Intput Inputs Cmd Code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area Data Input Address Inputs Address 85h Data Input ...
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... The 81h setup code is also accepted for backward compatibility. 28/69 input). IPBSY. Section 6.12). tIPBSY Busy 80h (1) 11h Address Inputs Confirm Multiplane Page A18=1 Code Program Setup code NAND04G-B2D, NAND08G-BxC Section 6.3.1: , the IPBSY tBLBH2 (Program Busy time) Busy Data Input 10h 70h SR0 Confirm Read Status Register Code ai13171b ...
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... The NAND04G-B2D and NAND08G-BxC devices feature automatic EDC during a copy back operation. Consequently, external ECC is no longer required. The errors detected ...
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... RB 6.6 Multiplane copy back program In addition to multiplane page program, the NAND04G-B2D and NAND08G-BxC devices support multiplane copy back program. A Multiplane Copy Back Program command requires exactly the same steps as a Multiplane Page Program command, and must satisfy the same time constraints (see Multiplane page program) ...
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... NAND04G-B2D, NAND08G-BxC Figure 17 provides a description of multiplane copy back program waveform. Figure 17. Multiplane copy back program Source I/O 35h 00h 00h Add Inputs Read Read A18=0 Code Code tBLBH1 (Read Busy time) RB Busy 1. The 81h setup code is also accepted for backward compatibility. 6.7 Block erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘ ...
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... D1h 60h Inputs Multiplane Block Block Erase A18 = 1 Erase Code Setup Code and Figure 20 for EDC unit addresses definition. NAND04G-B2D, NAND08G-BxC Figure 19: Multiplane block busy time is required between the tBLBH3 (Erase Busy time) Busy D0h 70h Confirm Read Status Code Register ...
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... NAND04G-B2D, NAND08G-BxC EDC results can be retrieved only during copy back program and multiplane copy back using the Read EDC Status Register command (see Figure 20. Page organization Main area (2048 bytes/1024 words) A area B area (512 bytes/ (512 bytes/ 256 words) 256 words) Table 12 ...
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... The error bit identifies if any errors have been detected by the P/E/R Controller. The error bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to ‘0’ the operation has completed successfully. 34/69 NAND04G-B2D, NAND08G-BxC Table 14: Status Register bits. Refer to Table 14 ...
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... NAND04G-B2D, NAND08G-BxC 6.11.5 SR4, SR3, SR2 and SR1 are reserved Table 14. Status Register bits Bit Name SR7 Write protection Program/Erase/Read SR6 Controller Program/Erase/Read SR5 Controller SR4, SR3, Reserved SR2, SR1 SR0 Generic error 1. Only valid for cache operations. 6.12 Read status enhanced In NAND Flash devices with multiplane architecture possible to independently read the Status Register of a single plane using the Read Status Enhanced command ...
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... Ready/busy ‘0’ ‘1’ (1) Ready/busy ‘0’ ‘1’ Write protect ‘0’ for a description of SR5 and SR6 bits. NAND04G-B2D, NAND08G-BxC Definition Copy back or multiplane copy back operation failed Copy back or multiplane copy back operation succeeded Error No error Valid Invalid ...
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... NAND04G-B2D, NAND08G-BxC Table 16. Electronic signature Root part number Byte 1 NAND04GR3B2D 20h (1) NAND08GR3B4C NAND04GW3B2D 20h (1) NAND08GW3B4C NAND04GR4B2D 0020h NAND04GW4B2D 0020h NAND08GR3B2C 20h NAND08GW3B2C 20h NAND08GR4B2C 0020h NAND08GW4B2C 0020h 1. For NAND08G-B4C devices, each 4 Gb die returns its own electronic signature. Table 17. Electronic signature byte 3 ...
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... I/O6 Table 19. Electronic signature byte 5 I/O I/O1 - I/O0 I/O3 - I/O2 I/O6 - I/O4 I/O7 38/69 Definition Page size time Block size Organization Definition Reserved Plane number Plane size (without spare area) Reserved NAND04G-B2D, NAND08G-BxC Value Description Kbytes Kbytes Kbytes Kbytes 30/ Reserved ...
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... NAND04G-B2D, NAND08G-BxC 6.15 Read ONFI signature To recognize NAND Flash devices that are compatible with the ONFI 1.0 command set, the Read Electronic Signature can be issued, followed by an address of 20h. The next four bytes output is the ONFI signature, which is the ASCII encoding of the “ONFI” word. ...
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... Device model (20 ASCII characters) M JEDEC manufacturer ID O Date code Reserved (0) M Number of data bytes per page M Number of spare bytes per page M Number of data bytes per partial page M Number of spare bytes per partial page M Number of pages per block NAND04G-B2D, NAND08G-BxC Description Revision number ...
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... NAND04G-B2D, NAND08G-BxC Table 21. Parameter page data structure (continued) Byte O/M 96-99 100 101 102 103-104 105-106 107 108-109 110 111 112 113 114 115-127 128 (1) M Number of blocks per logical unit (LUN) M Number of logical units (LUNs) Number of address cycles M Bit 4 to bit 7 Column address cycles ...
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... PROG M t maximum block erase time (µs) BERS M t maximum page read time (µ Reserved (0) M Vendor specific revision number M Vendor specific M Integrity CRC M Value of bytes 0-255 M Value of bytes 0-255 O Additional redundant parameter pages NAND04G-B2D, NAND08G-BxC Description ...
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... NAND04G-B2D, NAND08G-BxC 7 Concurrent operations and extended read status The NAND08G-BxC devices are composed of two 4-Gbit dice stacked together. This configuration allows the devices to support concurrent operations, which means that while performing an operation in one die (erase, read, program, etc.), another operation is possible in the other die. ...
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... Information may be erased. For the system to be able to recognize the bad blocks based on the original information, the creation of a bad block table following the flowchart shown in Figure 21: Bad block management flowchart 44/69 NAND04G-B2D, NAND08G-BxC Table 24: Program erase times and for the values) is recommended. ...
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... NAND04G-B2D, NAND08G-BxC 9.2 NAND Flash memory failure modes Over the lifetime of the device bad blocks may develop. To implement a highly reliable system, the possible failure modes must be considered. ● Program/erase failure In this case, the block has to be replaced by copying the data to a valid block. These additional bad blocks can be identified because attempts to program or erase them gives errors in the Status Register ...
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... The second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold. 46/69 Old Area New Area (After GC) Free Page (Erased) NAND04G-B2D, NAND08G-BxC AI07599B ...
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... NAND04G-B2D, NAND08G-BxC 9.5 Error correction code An ECC can be implemented in the NAND Flash memories to identify and correct errors in the data. For every 2048 bits in the device, the implementation of 22 bits of ECC (16 bits for line parity plus 6 bits for column parity) is recommended. Figure 23. Error detection ...
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... Multiplane Erase (1.8 V) Multiplane Program Busy time (t Multiplane Erase Busy time (t Cache Read Busy time (t Program/erase cycles per block (with ECC) Data retention 48/69 Min ) IPBSY ) IEBSY ) RCBSY 100 000 10 NAND04G-B2D, NAND08G-BxC NAND Flash Unit Typ Max 200 700 1 250 800 2 2 ...
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... NAND04G-B2D, NAND08G-BxC 11 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Input/output capacitances double in stacked devices. 50/69 Parameter ) Grade Grade 6 1.8 V device ) (1 TTL GATE L 3.0 V device ref (1) Parameter Test condition (2) IL and C are not 100% tested. IN I/O NAND04G-B2D, NAND08G-BxC NAND Flash Units Min Max 2.7 3 °C –40 85 ° 8.35 ...
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... NAND04G-B2D, NAND08G-BxC Figure 24. Equivalent testing circuit for AC characteristics measurement Table 28. DC characteristics (1.8 V devices) Symbol Parameter I DD1 Operating I current DD2 I DD3 I Standby current (CMOS DD5 I Input leakage current LI I Output leakage current LO V Input high voltage IH V Input low voltage IL V Output high voltage level ...
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... 2 0 Parameter AL setup time CL setup time Data setup time E setup time AL hold time CL hold time Data hold time E hold time W high hold time W pulse width Write cycle time NAND04G-B2D, NAND08G-BxC Min Typ Max - ± ± ...
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... NAND04G-B2D, NAND08G-BxC Table 31. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t BLBH2 PROG t t BLBH3 BERS Ready/Busy Low to Ready/Busy High t t BLBH4 RST ...
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... I/O 54/69 (1) (continued) is the delay from WP high to W High the delay from WP Low to W High. WW tWLWH tDVWH tWHDX (Data Setup time) (Data Hold time) Command NAND04G-B2D, NAND08G-BxC Min 100 Min 100 100 Figure 41, Figure 42 tWHCLL (CL Hold time) tWHEH (E Hold time) tWHALH (AL Hold time) ...
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... NAND04G-B2D, NAND08G-BxC Figure 26. Address latch AC waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH (AL Setup time) tWHALL (AL Hold time) AL tDVWH (Data Setup time) Adrress I/O cycle 1 Figure 27. Data input latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O 1. The last data input is the 2112th. ...
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... Data Out Data Out higher than 30ns). RLRL tRLRL tRHRL tRLQX tRLQV Data Out , and W is High lower than 30 ns). RLRL NAND04G-B2D, NAND08G-BxC tEHQX tEHQZ tRHQZ tRHQX (2) Data Out tEHQX tEHQZ tRHQZ tRHQX (2) Data Out Data Out ai13174 ai13175 ...
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... NAND04G-B2D, NAND08G-BxC Figure 30. Read Status Register or read EDC Status Register AC waveform CL tCLHWH E tELWH W R (Data Setup time) I/O Figure 31. Read status enhanced waveform I/O0-7 78h Address 1 tCLLRL tWHCLL tWHEH tWLWH tWHRL tDZRL tDVWH tWHDX (Data Hold time) 70h or 7Bh Address 2 Address 3 ...
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... ES Access time) 00h Byte1 Man. Device 1st Cycle code code Address tALLRL1 tRLQV (Read ES access time) 20h 4Fh 4Eh 1st cycle address NAND04G-B2D, NAND08G-BxC Byte2 Byte3 Byte4 Byte5 see Note.1 Table 17, Table 18, and Table 19 46h 49h XXh ai13178 for the ai13178b ...
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... NAND04G-B2D, NAND08G-BxC Figure 34. Page read operation AC waveform CL E tWLWL Add.N Add.N Add.N I/O 00h cycle 1 cycle 2 cycle 3 Command Address N Input Code tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N 30h N cycle 4 cycle 5 Busy from Address N to Last Byte or Word in Page ...
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... RB Page Program Setup Code 60/69 tWLWL tWHWH Add.N Add.N Add.N N cycle 4 cycle 5 cycle 3 Address Input Data Input NAND04G-B2D, NAND08G-BxC tWLWL tWHBL tWHRL tBLBH2 (Program Busy time) Last 10h 70h Confirm Page Code Program Read Status Register SR0 ai12475b ...
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... NAND04G-B2D, NAND08G-BxC Figure 36. Block erase AC waveform CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 37. Reset AC waveform I/O FFh RB tBLBH3 tWHBL (Erase Busy time) Add. Add. D0h cycle 2 cycle 3 Confirm Block Erase ...
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... DC and AC parameters Figure 38. Program/erase enable waveform W tVHWH WP RB I/O Figure 39. Program/erase disable waveform W tVLWH WP High RB I/O Figure 40. Read parameter page waveform I/O0-7 ECh R/B 62/69 80h 80h 00h tBLBH1 NAND04G-B2D, NAND08G-BxC 10h ai12477 10h ai12478 ... ... ai14409 ...
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... NAND04G-B2D, NAND08G-BxC 12.1 Ready/Busy signal electrical characteristics Figure 42, Figure 41 signal. The value required for the resistor R This is an example for 3 V devices: where I is the sum of the input currents of all the devices tied to the Ready/Busy signal max is determined by the maximum value of t Figure 41 ...
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... 64/ 3 200 2.4 150 1.2 100 100 50 50 1.8 1 the lower limit of nominal range, the WP pin should be kept LKO V LKO Locked Locked NAND04G-B2D, NAND08G-BxC 4 200 3 150 2 0.8 1 0.6 1.8 1 ibusy is below the V threshold. DD LKO Ai11086 ai12476 ...
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... NAND04G-B2D, NAND08G-BxC 13 Package mechanical Figure 45. TSOP48 - 48 lead plastic thin small outline mm, package outline DIE 1. Drawing is not to scale. Table 32. TSOP48 - 48 lead plastic thin small outline mm, package mechanical data Symbol Typ A A1 0.100 A2 1.000 B 0.220 12.000 E 20.000 E1 18 ...
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... A Millimeters Min Max 0.650 0.650 0.650 0.750 0.950 1.050 11.900 12.100 0.100 16.900 17.100 – – – – NAND04G-B2D, NAND08G-BxC FD1 BALL "A1" eE1 e ddd A2 LGA-9G Inches Typ Min 0.0256 0.0256 0.0276 0.0256 0.0295 0.0394 0.0374 0.0413 0.4724 0.4685 ...
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... B = 2112 byte page Device options 2 = Chip Enable ‘don't care’ enabled 4 = Chip Enable ‘don’t care’ enabled with dual interface Product version C= Third version (NAND08G-BxC Fourth version (NAND04G-B2D) Package N = TSOP48 LGA52 Temperature range ° – ...
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... Gbit devices as the NAND08G-BxC. Modified all data throughout this document to reflect the addition of these part numbers, namely: 2 – Table 1, Table 2, Table – Added Figure 5: LGA52 connections for the NAND08G-B4C devices. Changed V value in LKO 3 Applied Numonyx branding. NAND04G-B2D, NAND08G-BxC Changes 6, and Table 34. Table 28 from 1.1 to 1.2. ...
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... NAND04G-B2D, NAND08G-BxC INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...