NAND04G-B2D NUMONYX [Numonyx B.V], NAND04G-B2D Datasheet - Page 29

• Manufacturer Part Number: NAND04G-B2D
• Description: 4 Gbit, 8 Gbit, 2112 byte/1056 word page multiplane architecture, 1.8 V or 3 V, NAND Flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

NAND04G-B2D, NAND08G-BxC
6.5
Table 11.
Figure 14. Copy back program (without readout of data)
1. Copy back program is only permitted between odd address pages or even address pages.
RB
I/O
Read
Code
00h
Copy back program
The copy back program operation copies the data stored in one page and reprograms it in
another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
The NAND04G-B2D and NAND08G-BxC devices feature automatic EDC during a copy
back operation. Consequently, external ECC is no longer required. The errors detected
during copy back operations can be read by performing a read EDC Status Register
operation (see
EDC operations.
The copy back program operation requires the following four steps:
1.
2.
3.
To see the data input cycle for modifying the source page and an example of the copy back
program operation, refer to
Figure 16: Page copy back program with random data input
modify a portion or a multiple distant portion of the source page.
Copy back program addresses
The first step reads the source page. The operation copies all 2112 bytes from the
page into the data buffer. It requires:
–
–
–
When the device returns to the ready state (Ready/Busy High), optional data readout is
allowed by pulsing R; the next bus write cycle of the command is given with the 5 bus
cycles to input the target page address. See
the same for the source and target page.
Issue the confirm command to start the P/E/R Controller.
Add Inputs
Source
Density
One bus write cycle to set up the command
5 bus write cycles to input the source page address
One bus write cycle to issue the confirm command code
4 Gbits
8 Gbits
(Read Busy time)
Section 6.13: Read EDC Status
tBLBH1
35h
Busy
Figure 14: Copy back program (without readout of
Copy Back
Code
85h
Add Inputs
Target
Register). See also
Source and target page addresses
Table 11
(Program Busy time)
Same A18 and A30
for the addresses that must be
shows a data input cycle to
Same A18
tBLBH2
10h
Section 6.9
Busy
Read Status Register
Device operations
70h
data).
for details of
SR0
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