HYB18H1G321AF QIMONDA [Qimonda AG], HYB18H1G321AF Datasheet - Page 13

• Manufacturer Part Number: HYB18H1G321AF
• Description: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

3
3.1
The 1-Gbit GDDR3 incorporates a modified boundary scan test mode. This mode doesn’t operate in accordance with IEEE
Standard 1149.1-1990. To save the current GDDR3 ball-out, this mode will scan the parallel data input and output the scanned
data through the WDQS0 pin controlled by SEN.
Note: Both pads bCS1 and A12 will be activated and could be accessed during Boundary Scan.
3.2
It is possible to operate the 1-Gbit GDDR3 without using the boundary scan feature. SEN (at U-4 of 136- ball package) should
be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode,
RES, MF, WDQS0 and CS will be operating at normal GDDR3 functionalities when SEN is deasserted.
Notes
1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped.
2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67,
3. An unconnected CS1 and A12 on the board will be read as undefined.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
BIT#
1
2
3
4
5
6
7
8
9
10
11
12
if the chip stays in scan shift mode.
BALL
D-3
C-2
C-3
B-2
B-3
A-4
B-10
B-11
C-10
C-11
D-10
D-11
Boundary Scan
General Description
Disabling the scan feature
BIT#
13
14
15
16
17
18
19
20
21
22
23
24
BALL
E-10
F-10
E-11
G-10
F-11
G-9
H-9
H-10
H-11
J-11
J-10
L-9
BIT#
25
26
27
28
29
30
31
32
33
34
35
36
BALL
K-11
K-10
K-9
M-9
M-11
L-10
N-11
M-10
N-10
P-11
P-10
R-11
13
BIT#
37
38
39
40
41
42
43
44
45
46
47
48
BALL
R-10
T-11
T-10
T-3
T-2
R-3
R-2
P-3
P-2
N-3
M-3
N-2
BIT#
49
50
51
52
53
54
55
56
57
58
59
60
Boundary Scan Exit Order
HYB18H1G321AF–10/11/14
BALL
L-3
M-2
M-4
K-4
K-3
K-2
L-4
J-3
J-2
H-2
H-3
H-4
Internet Data Sheet
BIT#
61
62
63
64
65
66
67
1-Gbit GDDR3
TABLE 6
BALL
G-4
F-4
F-2
G-3
E-2
F-3
E-3