HYB18H1G321AF QIMONDA [Qimonda AG], HYB18H1G321AF Datasheet - Page 18

• Manufacturer Part Number: HYB18H1G321AF
• Description: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

4.1.1
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length of 4 and 8. This value must be
programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column locations
that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses
for that burst take place within this block if a boundary is reached. The starting location within this block is determined by the
two least significant bits A0 and A1 which are set internally to the fixed value of zero each.Reserved states should not be used,
as unknown operation or incompatibility with future versions may result.
4.1.2
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3).
This device does not support the burst interleave mode.
The value applied at the balls A0 and A1 for the column address is “Don’t care”.
4.1.3
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit
of output data.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident
with clock edge n+m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
4.1.4
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the
first bit of input data.
4.1.5
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and
A8-A11 set to the desired value.
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Burst Length
4
8
A2 A1 A0
— X
0
1
Starting Column Address
Burst length
Burst type
CAS Latency
Write Latency
Test mode
X
X
X
X
X
Order of Accesses within a Burst
(Type = sequential)
0-1-2-3
0-1-2-3-4-5-6-7
4-5-6-7-0-1-2-3
18
HYB18H1G321AF–10/11/14
Internet Data Sheet
Burst Definition
1-Gbit GDDR3
TABLE 8