HYB18H1G321AF QIMONDA [Qimonda AG], HYB18H1G321AF Datasheet - Page 14

• Manufacturer Part Number: HYB18H1G321AF
• Description: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

Notes
1. When SEN is asserted, no commands are to be executed by the GDDR3. This applies both to user commands and
2. The Scan Function can be used right after bringing up
3. In Scan Mode all terminations for CMD/ADD and DQ, DM, RDQS and WDQS are switched off.
4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE’s should be provided to
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
PACKAGE
BALL
V-9
F-9
D-2
V-4
A-9
manufacturing commands which may exist while RES is deasserted.
required. After leaving the Scan Function it is required to run through the complete initialization sequence.
top and bottom devices to access the scanned output. When either of the devices is in scan mode, SOE for the other device
which is not in a scan will be disabled.
SYMBOL
SSH
SCK
SOUT
SEN
SOE
NORMAL
FUNCTION
RES
CS
WDQS0
SEN
MF
TYPE
Input
Input
Output Scan Output
Input
Input
DESCRIPTION
Scan Shift: Capture the data input from the pad at logic LOW and shift the
data on the chain at logic HIGH.
Scan Clock: Not a true clock, could be a single pulse or series of pulses.
All scan inputs will be referenced to rising edge of the scan clock
Scan Enable: Logic HIGH enables the device into scan mode and will be
disabled at logic LOW. Must be tied to GND when not in use.
Scan Output Enable: Enables (registered LOW) and disables (registered
HIGH) SOUT data. This pin will be tied to
(typically 1KΩ for normal operation. Tester needs to overdrive this pin to
guarantee the required input logic level in scan mode.
V
DD
14
/
V
DDQ
of the device. No initialization sequence of the device is
V
DD
HYB18H1G321AF–10/11/14
or GND through a resistor
Scan Pin Description
Internet Data Sheet
1-Gbit GDDR3
TABLE 7