HYB18H1G321AF QIMONDA [Qimonda AG], HYB18H1G321AF Datasheet - Page 9

• Manufacturer Part Number: HYB18H1G321AF
• Description: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.2
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF. This function
allows for efficient routing in a clam shell configuration.
Depending of the logic state applied on MF, the command and address signals will be assigned to different balls. The default
ball configuration (see
The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that.
Table 3
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Ball
BA<0:2>
A<0:11>
A<12>
ZQ
RESET
MF
SEN
V
V
V
NC, RFU
RAR
REF
DD
DDQ
,
V
,
V
SS
SSQ
shows the ball assignment as a function of the logic state applied on MF.
Type
Input
Input
-
Input
-
Input
Input
Input
Supply Voltage Reference:
Supply Power Supply:
Supply I/O Power Supply:
Mirror Function
Figure
Detailed Function
Bank Address Inputs:
BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being
applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED
MODE REGISTER SET commands.
Address Inputs:
During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the
column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is
precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and
the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is
precharged (selected by BA<0:2>, A8 LOW) or all 8 banks are precharged (A8 HIGH). During
(EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are
sampled with the positive edge of CLK.
Address Inputs:
A12 define the MSB of the row address during an ACTIVATE in 1-CS mode.
ODT Impedance Reference:
The ZQ ball is used to control the ODT impedance.
Reset pin:
The RES pin is a
chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High
transition of the RES signal is used to latch the CKE value to set the value of the termination resistors
of the address and command inputs. After exiting the full reset a complete initialization is required
since the full reset sets the internal settings to default.
Mirror function pin:
The MF pin is a
ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow
for an easier routing on board for a back to back memory arrangement.
Enables Boundary Scan Functionality:
V
Power and Ground for the internal logic.
Isolated Power and Ground for the output buffers to provide improved noise immunity.
Please do not connect No Connect and Reserved for Future Use balls.
Reserved for Alternate Rank
If Boundary Scan is not used PIN should be constantly connected to GND.
REF
2) corresponds to MF = LOW. The CS1 and A12 balls are not mirrored.
is the reference voltage input.
V
V
DDQ
DDQ
CMOS input. This pin must be hardwired on board either to a power or to a
CMOS input. RES is not internally terminated. When RES is at LOW state the
9
HYB18H1G321AF–10/11/14
Internet Data Sheet
1-Gbit GDDR3