AT90USB1286-16MU ATMEL [ATMEL Corporation], AT90USB1286-16MU Datasheet - Page 100

• Manufacturer Part Number: AT90USB1286-16MU
• Description: Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
• Manufacturer: ATMEL [ATMEL Corporation]

12.4
100
General Timer/Counter Control Register – GTCCR
AT90USB64/128
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 2. Prescaler for synchronous Timer/Counters
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1, Timer/Counter3, Timer/Counter4 and
Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware,
except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1, Timer/Counter3,
Timer/Counter4 and Timer/Counter5 share the same prescaler and a reset of this prescaler will
affect all timers.
Bit
Read/Write
Initial Value
PSR10
clk
CSn0
CSn1
CSn2
Tn
Tn
I/O
Synchronization
Synchronization
7
TSM
R/W
0
6
–
R
0
ExtClk
< f
TIMER/COUNTERn CLOCK SOURCE
5
–
R
0
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
4
–
R
0
clk
Clear
Tn
3
–
R
0
2
–
R
0
CSn0
CSn1
CSn2
1
PSRA-
SY
R/W
0
TIMER/COUNTERn CLOCK SOURCE
0
PSRSY
NC
R/W
0
clk
Tn
GTCCR
clk_I/O
7593A–AVR–02/06
/2.5.