AT90USB1286-16MU ATMEL [ATMEL Corporation], AT90USB1286-16MU Datasheet - Page 279

• Manufacturer Part Number: AT90USB1286-16MU
• Description: Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
• Manufacturer: ATMEL [ATMEL Corporation]

22.16.2
22.17 Overflow
22.18 Interrupts
7593A–AVR–02/06
CRC Error
An underflow can also occur during OUT stage if the host send a packet while the banks are
already full. Typically, he CPU is not fast enough. The packet is lost.
It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU
should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)
A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt
from being triggered.
In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if
the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI
interrupt is triggered (if enabled). The packet is hacknowledged and the RXOUTI interrupt is also
triggered (if enabled). The bank is filled with the first bytes of the packet.
It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should
write only if the bank is ready to access data (TXINI=1 or RWAL=1).
The next figure shows all the interrupts sources:
Figure 22-4. USB Device Controller Interrupt System
There are 2 kind of interrupts: processing (i.e. their generation are part of the normal processing)
and exception (errors).
Processing interrupts are generated when:
• VBUS plug-in detection (insert, remove)(VBUSTI)
• Upstream resume(UPRSMI)
• End of resume(EORSMI)
• Wake up(WAKEUPI)
• End of reset (Speed Initialization)(EORSTI)
UPRSMI
UDINT.6
EORSMI
UDINT.5
WAKEUPI
UDINT.4
UDINT.3
UDINT.2
UDINT.0
EORSTI
SUSPI
SOFI
EORSME
UPRSME
WAKEUPE
UDIEN.6
UDIEN.5
UDIEN.4
EORSTE
UDIEN.3
UDIEN.2
UDIEN.0
SUSPE
SOFE
USB Device
AT90USB64/128
Interrupt
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