AT90USB1286-16MU ATMEL [ATMEL Corporation], AT90USB1286-16MU Datasheet - Page 22
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AT90USB1286-16MU
Manufacturer Part Number
AT90USB1286-16MU
Description
Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT90USB1286-16MU.pdf
(434 pages)
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5.3
5.3.1
5.3.2
22
EEPROM Data Memory
AT90USB64/128
EEPROM Read/Write Access
The EEPROM Address Register – EEARH and EEARL
Figure 5-3.
The AT90USB64/128 contains 2K/4K bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page 27.
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
Bit
382,
page
CC
Address
15
–
EEAR7
clk
is likely to rise or fall slowly on power-up/down. This causes the device for some
On-chip Data SRAM Access Cycles
Data
Data
387, and
WR
CPU
RD
14
–
EEAR6
page 371
Compute Address
13
–
EEAR5
T1
Memory Access Instruction
respectively.
12
–
EEAR4
11
EEAR11
EEAR3
Address valid
for details on how to avoid problems in these
T2
Table
10
EEAR10
EEAR2
5-3. A self-timing function, however,
9
EEAR9
EEAR1
Next Instruction
T3
8
EEAR8
EEAR0
EEARH
EEARL
7593A–AVR–02/06
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