AT90USB1286-16MU ATMEL [ATMEL Corporation], AT90USB1286-16MU Datasheet - Page 118
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AT90USB1286-16MU
Manufacturer Part Number
AT90USB1286-16MU
Description
Microcontroller with 64/128K Bytes of ISP Flash and USB Controller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT90USB1286-16MU.pdf
(434 pages)
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14. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
14.1
118
Overview
AT90USB64/128
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
•
•
•
•
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Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
placement of I/O pins, see
isters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the
118.
The Power Reduction Timer/Counter1 bit, PRTIM1, in
page 55
The Power Reduction Timer/Counter3 bit, PRTIM3, in
page 56
True 16-bit Design (i.e., Allows 16-bit PWM)
Three independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Twenty independent interrupt sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A,
OCF3B, OCF3C, ICF3, TOV4, OCF4A, OCF4B, OCF4C, ICF4, TOV5, OCF5A, OCF5B, OCF5C and
ICF5)
must be written to zero to enable Timer/Counter1 module.
must be written to zero to enable Timer/Counter3 module.
“16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page
“Pinout AT90USB64/128-TQFP” on page
“Power Reduction Register 0 - PRR0” on
“Power Reduction Register 1 - PRR1” on
3. CPU accessible I/O Reg-
Figure
14-1. For the actual
7593A–AVR–02/06
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