MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 115

• Manufacturer Part Number: MC908JL16CFAE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.7 MMIIC During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
8.8 Multi-Master IIC Registers
Six registers are associated with the Multi-master IIC module, they are outlined in the following sections.
8.8.1 Multi-Master IIC Address Register (MMADR)
MMAD[7:1] — Multi-Master Address
MMEXTAD — Multi-Master Expanded Address
For example, when MMADR is configured as:
Freescale Semiconductor
These seven bits represent the MMIIC interface’s own specific slave address when in slave mode, and
the calling address when in master mode. Software must update MMAD[7:1] as the calling address
while entering master mode and restore its own slave address after master mode is relinquished. This
register is cleared as $A0 upon reset.
This bit is set to expand the address of the MMIIC in slave mode. When set, the MMIIC will
acknowledge the following addresses from a calling master: $MMAD[7:1], 0000000, and 0001100.
Reset clears this bit.
1 = MMIIC responds to the following calling addresses:
0 = MMIIC responds to address $MMAD[7:1]
$MMAD[7:1], 0000000, and 0001100.
Address: $0041
Reset:
Read:
Write:
MMAD7
1
Figure 8-4. Multi-Master IIC Address Register (MMADR)
MMAD7
Bit 7
1
MMAD6
1
MMAD6
6
0
MC68HC908JL16 Data Sheet, Rev. 1.1
MMAD5
0
MMAD5
5
1
MMAD4
1
MMAD4
4
0
MMAD3
0
MMAD3
3
0
MMAD2
1
MMAD2
sheet.
2
0
MMAD1
0
MMAD1
MMIIC During Break Interrupts
1
0
MMEXTAD
1
MMEXTAD
Bit 0
0
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