MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 118

• Manufacturer Part Number: MC908JL16CFAE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Multi-Master IIC Interface (MMIIC)
MMBR2–MMBR0 — Baud Rate Select
8.8.4 Multi-Master IIC Status Register (MMSR)
MMRXIF — Multi-Master IIC Receive Interrupt Flag
MMTXIF — Multi-Master Transmit Interrupt Flag
MMATCH — Multi-Master Address Match
118
These three bits select one of eight clock rates as the master clock when the module is in master mode.
Since this master clock is derived the CPU bus clock, the user program should not execute the WAIT
instruction when the MMIIC module in master mode. This will cause the SDA and SCL lines to hang,
as the WAIT instruction places the MCU in wait mode, with CPU clock is halted. These bits are cleared
upon reset. (See
This flag is set after the data receive register (MMDRR) is loaded with a new received data. Once the
MMDRR is loaded with received data, no more received data can be loaded to the MMDRR register
until the CPU reads the data from the MMDRR to clear MMRXBF flag. MMRXIF generates an interrupt
request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset;
or when the MMEN = 0.
This flag is set when data in the data transmit register (MMDTR) is downloaded to the output circuit,
and that new data can be written to the MMDTR. MMTXIF generates an interrupt request to CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or when the MMEN = 0.
This flag is set when the received data in the data receive register (MMDRR) is an calling address
which matches with the address or its extended addresses (MMEXTAD=1) specified in the MMADR
register.
1 = New data in data receive register (MMDRR)
0 = No data received
1 = Data transfer completed
0 = Data transfer in progress
1 = Received address matches MMADR
0 = Received address does not match
Address: $0043
Reset:
Read: MMRXIF
Write:
Table 8-2.)
MMBR2
Bit 7
Figure 8-7. Multi-Master IIC Status Register (MMSR)
0
0
0
0
0
0
1
1
1
1
= Unimplemented
MMTXIF
MMBR1
6
0
0
MC68HC908JL16 Data Sheet, Rev. 1.1
0
0
1
1
0
0
1
1
Table 8-2. Baud Rate Select
MMATCH
5
0
MMBR0
0
1
0
1
0
1
0
1
MMSRW
4
0
MMRXAK
Internal bus clock ÷ 1024
Internal bus clock ÷ 128
Internal bus clock ÷ 256
Internal bus clock ÷ 512
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Internal bus clock ÷ 8
3
1
Baud Rate
2
0
0
MMTXBE
1
1
Freescale Semiconductor
MMRXBF
Bit 0
0