MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 51

• Manufacturer Part Number: MC908JL16CFAE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V
trip voltage V
held low while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls
down the RST pin for all internal reset sources.
4.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of ICLK.
4.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
4.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay
of 4096 ICLK cycles down to 32 ICLK cycles. This is ideal for applications using canned oscillators that
do not require long start-up times from stop mode. External crystal applications should use the full stop
recovery time, that is, with SSREC cleared in the configuration register 1 (CONFIG1).
4.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See
free-running after all reset states. (See
internal reset recovery sequences.)
4.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
4.5.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 4-8
Freescale Semiconductor
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•
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Interrupts
–
–
Reset
Break interrupts
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
flow charts the handling of system interrupts.
TRIP
. The LVI bit in the reset status register (RSR) is set, and the external reset pin (RST) is
MC68HC908JL16 Data Sheet, Rev. 1.1
4.3.2 Active Resets from Internal Sources
4.6.2 Stop Mode
for details.) The SIM counter is
DD
voltage falls to the LVI
for counter control and
SIM Counter
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