MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 186

• Manufacturer Part Number: MC908JL16CFAE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Development Support
16.3.2 Entering Monitor Mode
Table 16-1
may be entered after a POR.
Communication at 9600 baud will be established provided one of the following sets of conditions is met:
If V
frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with V
monitor mode entry
to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two
stage at the oscillator only if V
2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
Entering monitor mode with V
RST. (See
If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF)
(Table 16-1
including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements
when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the
state of IRQ or the RST.
186
1. RC oscillator cannot be used for monitor mode; must use either external oscillator or XTAL oscillator circuit.
2. See
1. If IRQ = V
2. If IRQ = V
3. If $FFFE and $FFFF are blank (contain $FF):
V
V
TST
TST
TST
V
V
IRQ
DD
DD
–
–
–
–
–
–
(2)
(1)
Table 17-4
is applied to IRQ and PTB3 is low upon monitor mode entry
Clock on OSC1 is 4.9125MHz
PTB3 = low
Clock on OSC1 is 9.8304MHz
PTB3 = high
Clock on OSC1 is 9.8304MHz
IRQ = V
Chapter 4 System Integration Module (SIM)
shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
condition set 3, where applied voltage is V
(contain
BLANK
BLANK
$FFFE
$FFFF
$FF)
NOT
and
TST
TST
for V
X
X
DD
:
:
(Table 16-1
Table 16-1. Monitor Mode Entry Requirements and Options
TST
voltage level requirements.
X
X
0
1
0
0
X
X
TST
TST
condition set 2), the bus frequency is a divide-by-four of the clock input
on IRQ, the COP is disabled as long as V
X
X
1
1
is applied to IRQ. In this event, the OSCOUT frequency is equal to the
MC68HC908JL16 Data Sheet, Rev. 1.1
X
1
1
1
OSC1 Clock
4.9152MHz
9.8304MHz
9.8304MHz
X
DD
(1)
for more information on modes of operation.)
), then all port B pin requirements and conditions,
Bus Frequency
2.4576MHz
2.4576MHz
2.4576MHz
OSC1 ÷ 4
(Table 16-1
TST
TST
is applied to either IRQ or
9600 baud communication on
9600 baud communication on
(low-voltage) entry to monitor
High voltage entry to monitor
condition set 1), the bus
PTB0. COP disabled.
PTB0. COP disabled.
applied to IRQ upon
Enters User mode.
Freescale Semiconductor
Blank reset vector
Comments
mode.
mode.