MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 92

• Manufacturer Part Number: MC908JL16CFAE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Communications Interface (SCI)
7.4.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following
times (see
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 7-2
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
92
•
•
RT CLOCK
RT CLOCK
SAMPLES
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
CLOCK
RESET
STATE
RxD
summarizes the results of the start bit verification samples.
Figure
RT
7-6):
RT3, RT5, and RT7
QUALIFICATION
Samples
START BIT
Figure 7-6. Receiver Data Sampling
000
001
010
011
100
101
110
111
MC68HC908JL16 Data Sheet, Rev. 1.1
Table 7-2. Start Bit Verification
VERIFICATION
START BIT
Verification
Start Bit
Yes
Yes
Yes
Yes
No
No
No
No
START BIT
SAMPLING
DATA
Noise Flag
0
1
1
0
1
0
0
0
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