MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 156
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MC9S12E32CFU
Manufacturer Part Number
MC9S12E32CFU
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12E32CFU.pdf
(606 pages)
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Chapter 3 Port Integration Module (PIM9E128V1)
3.3.7.3
Read: Anytime. Write: Anytime.
This register configures port pins PU[7:0] as either input or output.
If a pulse width modulator channel is enabled, the associated pin is forced to be an output and the
associated Data Direction Register bit has no effect. If the associated pulse width modulator channel is
disabled, the corresponding DDRUx bit reverts to control the I/O direction of the associated pin.
If the TIM2 module is enabled, each port pin configured for output compare is forced to be an output and
the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled,
the corresponding DDRUx bit reverts to control the I/O direction of the associated pin.
If the TIM2 module is enabled, each port pin configured as an input capture has the corresponding DDRUx
bit controlling the I/O direction of the associated pin.
When both a timer function and a PWM function are enabled on the same pin, the MODRR register
determines which function has control of the pin
156
DDRU[7:0]
Reset
Field
7:0
W
R
DDRU7
Data Direction Port U
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port U Data Direction Register (DDRU)
0
7
DDRU6
0
6
Figure 3-44. Port U Data Direction Register (DDRU)
Table 3-31. DDRT Field Descriptions
DDRU5
MC9S12E128 Data Sheet, Rev. 1.07
0
5
DDRU4
0
4
Description
DDRU3
0
3
DDRU2
0
2
DDRU1
Freescale Semiconductor
0
1
DDRU0
0
0
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