MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 379

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MC9S12E32CFU

Manufacturer Part Number
MC9S12E32CFU
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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11.5
All PWM registers are reset to their default values upon any system reset.
11.6
The system bus clock is the only clock required by this module.
Freescale Semiconductor
Resets
Clocks
PWM half-cycle boundaries occur at both the PWM cycle start and when the
counter equals the modulus, so in edge-aligned operation full-cycles and
half-cycles are equal.
Fault protection also applies during software output control when the
OUTCTLx bits are set. Fault clearing still occurs at half PWM cycle
boundaries while the PWM generator is engaged, PWMEN equals one. But
the OUTx bits can control the PWM pins while the PWM generator is off,
PWMEN equals zero. Thus, fault clearing occurs at IPbus cycles while the
PWM generator is off and at the start of PWM cycles when the generator is
engaged.
FAULT0 OR
FAULT1 OR
Figure 11-78. Manual Fault Clearing (Faults 0 & 2) - QSMP=01, 10, or 11
FAULT2
FAULT3
PWMS ENABLED
PWMS ENABLED
Figure 11-79. Manual Fault Clearing (Faults 1 & 3)
MC9S12E128 Data Sheet, Rev. 1.07
PWMS DISABLED
CLEARED
CLEARED
PWMS DISABLED
FFLAGx
FFLAGx
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
NOTE
NOTE
PWMS ENABLED
PWMS ENABLED
379

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