MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 428

• Manufacturer Part Number: MC9S12E32CFU
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 13 Timer Module (TIM16B4CV1)
13.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
13.3.2.11 Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
428
C7I:C0I
PR[2:0]
Reset
Reset
TCRE
Field
Field
TOI
7:4
7
3
2
W
W
R
R
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF
will never be set when TCNT is reset from 0xFFFF to 0x0000.
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in
C7I
TOI
0
0
7
7
= Unimplemented or Reserved
C6I
Figure 13-17. Timer System Control Register 2 (TSCR2)
0
0
0
6
6
Figure 13-16. Timer Interrupt Enable Register (TIE)
Table
Table 13-13. TSCR2 Field Descriptions
Table 13-12. TIE Field Descriptions
13-14.
MC9S12E128 Data Sheet, Rev. 1.07
C5I
0
0
0
5
5
C4I
0
0
0
4
4
Description
Description
TCRE
0
0
0
3
3
PR2
0
0
0
2
2
Freescale Semiconductor
PR1
0
0
0
1
1
PR0
0
0
0
0
0