M52S64322A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52S64322A-10BG Datasheet - Page 14
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M52S64322A-10BG
Manufacturer Part Number
M52S64322A-10BG
Description
512K x 32 Bit x 4 Banks Mobile Synchronous DRAM
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
1.M52S64322A-10BG.pdf
(47 pages)
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COMMANDS
Mode register set command
this command, A0 through BA0 are the data input pins. After power on, the mode
register set command must be executed to initialize the device.
(t
Extended Mode register set command
TCSR, DS.
Activate command
address selected by A0 through A10.
Elite Semiconductor Memory Technology Inc.
MRD
The M52S64322A has a mode register that defines how the device operates. In
The mode register can be set only when all banks are in idle state. During 2CLK
The M52S64322A has a extended mode register that defines how to set PASR,
The M52S64322A has four banks, each with 2,048 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
This command corresponds to a conventional DRAM’s RAS falling.
) following this command, the M52S64322A cannot accept any other commands.
(
( CS , RAS , CAS , WE , BA0 = Low ; BA1= High)
( CS , RAS = Low, CAS , WE = High)
CS
,
RAS
,
CAS
,
WE
,
BA1, BA0 = Low)
Publication Date: Aug. 2009
Revision: 1.3
M52S64322A
14/47
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