M52S64322A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52S64322A-10BG Datasheet - Page 43
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M52S64322A-10BG
Manufacturer Part Number
M52S64322A-10BG
Description
512K x 32 Bit x 4 Banks Mobile Synchronous DRAM
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
1.M52S64322A-10BG.pdf
(47 pages)
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ESMT
Self Refresh Entry & Exit Cycle
* Note:
Elite Semiconductor Memory Technology Inc.
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh
cf.) Once the device enters self refresh mode, minimum t
exit.
RFC
is required after CKE going high to complete self refresh exit.
RAS
is required before exit from self refresh.
Publication Date: Aug. 2009
Revision: 1.3
M52S64322A
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