M52S64322A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52S64322A-10BG Datasheet - Page 5
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M52S64322A-10BG
Manufacturer Part Number
M52S64322A-10BG
Description
512K x 32 Bit x 4 Banks Mobile Synchronous DRAM
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
1.M52S64322A-10BG.pdf
(47 pages)
AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
Elite Semiconductor Memory Technology Inc.
RAS to CAS delay
Row active time
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or Refresh
Command
Refresh period(4K cycle)
Number of valid output
data
5. A new command may be given t
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
6. A maximum of eight consecutive AUTO REFRESH commands (with t
then rounding off to the next higher integer.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)
Parameter
Parameter
@ Operating
@ Auto refresh
CAS latency=3
CAS latency=2
RFC
after self refresh exit.
(V
DD
=2.5V
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
RRD
RCD
RP
RAS
RAS
RC
RFC
CDL
RDL
BDL
CCD
MRD
REF
(min)
(min)
(min)
(min)
(min)
(max)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
±
0.2V, T
A
0.9 x V
= 0 C
tr / tf = 1 / 1
0.5 x V
0.5 x V
See Fig.2
° ~ 70 C
Value
-7.5
15
20
20
45
75
75
DDQ
DDQ
DDQ
RFCmin
/ 0.2
Version
° )
100
64
1
2
1
1
2
2
1
) can be posted to any given SDRAM, and
100
100
-10
20
30
30
50
Publication Date: Aug. 2009
Revision: 1.3
M52S64322A
Unit
CLK
CLK
CLK
CLK
CLK
ms
ns
ns
ns
ns
us
ns
ns
ea
Unit
ns
V
V
V
Note
1 , 5
1
1
5/47
1
1
1
2
2
2
3
6
4
-
-