XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 40

• Manufacturer Part Number: XC68HC05P18A
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

Interrupts
4.3 CPU Interrupt Processing
Technical Data
40
Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
completed.
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear), and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The SWI is executed the
same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$3FF0–$3FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location, shown in
Table
A return-from-interrupt (RTI) instruction is used to signify when the
interrupt software service routine is completed. The RTI instruction
Register
TSR
TSR
TSR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4-1, is serviced first.
Table 4-1. Vector Address for Interrupts and Reset
Name
OCF
Flag
TOF
N/A
N/A
N/A
ICF
N/A
N/A
N/A
N/A
Interrupts
Reset
Software
External interrupt
Timer input capture
Timer output compare
Timer overflow
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Interrupts
Interrupt
RESET
TIMER
TIMER
TIMER
CPU
SWI
IRQ
N/A
N/A
N/A
N/A
Vector Address
$3FFC–$3FFD
$3FFE–$3FFF
$3FFA–$3FFB
$3FF8–$3FF9
$3FF8–$3FF9
$3FF8–$3FF9
$3FF6–$3FF7
$3FF4–$3FF5
$3FF2–$3FF3
$3FF0–$3FF1
MC68HC05P18A
MOTOROLA